Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - DDR I

Search list

[Other resource] ddr

Description: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Platform: | Size: 2317 | Author: 孙强 | Hits:

[VHDL-FPGA-Verilog] ddr

Description: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Platform: | Size: 2048 | Author: 孙强 | Hits:

[VHDL-FPGA-Verilog] ddr

Description: ISE MIG1.6 生成的DDR SDRAM控制器代码（含TESHBENCH）
Platform: | Size: 1022976 | Author: yuling | Hits:

[Software Engineering] DDR_SDRAM

Description: 该项对于设计DDSRAM有很大的帮助，希望可以对你有所帮助。-For the design of the DDSRAM have great help, I hope you can help.
Platform: | Size: 474112 | Author: 王辉 | Hits:

[Software Engineering] mx27ads_x33

Description: i.mx27开发板的整套详细原理图，包括：DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST,FEC PHY, UART,JTAG等等接口-i.MX27 development board schematic details of the package, including: DDR SDRAM, NAND FLASH, NOR FLASH, USB OTG, USB HOST, FEC PHY, UART, JTAG interface, etc.
Platform: | Size: 741376 | Author: 清木 | Hits:

[Embeded Linux] nandboot

Description: mx27 bootloader nandboot cpu:i.mx27 nand:K9F2G08U0A ddr:HYB18M1G320BF-7[1][1].5
Platform: | Size: 94208 | Author: 任浩然 | Hits:

[Other] yuqix_datum

Description: i2cinterface.v是我自己写的一段verilog代码，在接口为I2C接口的芯片设计中用到。送去流过片，仅作参考用。 debussy和modelsim协同仿真.txt 用于debussy和modelsim协同仿真时参考 RTL Coding and Optimization Guide for use with Design Compiler.pdf 数提讲座（1）.wmv 数提讲座（2）.wmv这两个视频和一篇文档对数字IC前端设计师的设计提高很有帮助，如果你觉得你到瓶颈状态了，想提高的话，强烈建议好好看看。 ADVANCED ASIC CHIP SYNTHESIS中文翻译资料.ppt这也是我极力推荐的，相信学习dc的人都知道原英文文档。这个ppt相当于翻译版，对dc和pt中文详细阐述。 基于DDR SDRAM控制时序分析的模型.pdf 全定制单元时序模型的建立.pdf 这两篇文档是用作建议时序模型的时候用作参考，是我花了小money买的哦。 数字IC设计全程实例.pdf 本文介绍了基于标准单元库的深亚微米数字集成电路的自动化设计流程。此流程从设计的系统行为级描述或RTL 级描述开始，依次通过系统行为级的功能验证，设计综合，综合后仿真，自动化布局布线，到最后的版图后仿真. -i2cinterface.v a section of my own writing verilog code for the I2C interface in the interface used in chip design. Sent to flow through the film, only for reference. debussy and modelsim co-simulation. txt for debussy and modelsim co-simulation reference RTL Coding and Optimization Guide for use with Design Compiler.pdf Mention the number of lectures (1). Wmv Mention the number of lectures (2). Wmv the two videos, and the document is useful for the digital front-end IC designers to improve the design capability. if you think you go to bottleneck, and want to improve, then it is strongly recommended a good look. ADVANCED ASIC CHIP SYNTHESIS Chinese translation of the information. Ppt that is what I strongly recommend, I believe that everyone learning dc knows its original English document. This ppt is equivalent to its translations.It elaborates the dc and pt in Chinese . DDR SDRAM control the timing analysis based on the model. Pdf
Platform: | Size: 20989952 | Author: 喻琪 | Hits:

[VHDL-FPGA-Verilog] c_xapp858

Description: 这是xilinx应用指南xapp858的中文版本。本应用指南介绍了用于实现高性能 DDR2 SDRAM 接口的控制器和数据采集技术。本数据采集技术使用了每一个 Virtex™ -5 I/O 都具有的输入串行器/ 解串器 (ISERDES) 和输出双倍数据速率 (ODDR) 的功能。-This is the xilinx application note xapp858 the Chinese version. This application note describes the interface used to achieve high-performance DDR2 SDRAM controller and data acquisition technology. This data collection technique used in each Virtex ™ -5 I/O has an input serializer/deserializer (ISERDES) and output double data rate (ODDR) function.
Platform: | Size: 447488 | Author: 陈阳 | Hits:

[Software Engineering] S5PC100_UM_REV1.04

Description: Samsung s new ARM cpu datasheet. S5PC100 Spec. - CPU ARM Cortex-A8 667-833Mhz - 32KB L1, 256KB L2 Cache - Video 720p (1280x720 Play. h.264 divx, mp4...) - nand, sd/mmc, usb booting - Windows CE 6.0, Linux (*Android) support - support 166MHz memory clock. DDR, mobileDDR, DDR2 * in actually, i run c100 board ddr2 bus clock at 280MHz in WinCE 6.0
Platform: | Size: 12115968 | Author: john | Hits:

[VHDL-FPGA-Verilog] ddr_100Mhz_2011.03.12

Description: 这个工程是用xilinx的MIG生成的对于spartan 3E的实验板的ddr的控制器，我已经能够在上面修改之后加入自己的思想，包括两个dcm的模块。-This project is the MIG generated by xilinx spartan 3E development board for the ddr controller, I have been able to modify the above by adding his own ideas, including the two dcm module.
Platform: | Size: 6132736 | Author: 张元甲 | Hits:

[Other] MYmcb_read_write

Description: 自己编写的一个赛灵思读写DDR的代码，可以正常读写DDR。-I have written a Xilinx DDR write code that can read and write normal DDR.
Platform: | Size: 2048 | Author: 王超 | Hits:

[Delphi VCL] nexys4-ddr_sw_demo

Description: The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) Xilinx® . With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C), generous external memories, and collection of USB, Ethernet, and other ports, the Nexys4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, a speaker amplifier, and several I/O devices allow the Nexys4 DDR to be used for a wide range of designs without needing any other component-The Nexys4 DDR board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) Xilinx® . With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C), generous external memories, and collection of USB, Ethernet, and other ports, the Nexys4 DDR can host designs ranging from introductory combinational circuits to powerful embedded processors. Several built-in peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, a speaker amplifier, and several I/O devices allow the Nexys4 DDR to be used for a wide range of designs without needing any other component
Platform: | Size: 1024 | Author: yaseenn | Hits:

[android] I.MX6DQSDL-DDR3-Script-Aid-V0.10

Description: 飞思卡尔平台imx6 DDR配置参数配置工具。-Freescale platform imx6 DDR configuration parameter configuration tool.
Platform: | Size: 89088 | Author: 谢志鹏 | Hits:

[VHDL-FPGA-Verilog] source

Description: 2. /qdr2/source/qdr2_io.v > Top level file includes declarations of HSTL1 and LVTTL I/O standards /qdr2/source/qdr2.v > Main module of the QDR memory controller /qdr2/source/pipeline.v > Pipeline module for increasing performance /qdr2/source/oddr_xp.v > Output DDR module /qdr2/source/pll_qdr_sim.v > Pll module for simulation /qdr2/source/pll_qdr_syn.v > Pll module for synthesis /qdr2/source/magma.v- 2. /qdr2/source/qdr2_io.v > Top level file includes declarations of HSTL1 and LVTTL I/O standards /qdr2/source/qdr2.v > Main module of the QDR memory controller /qdr2/source/pipeline.v > Pipeline module for increasing performance /qdr2/source/oddr_xp.v > Output DDR module /qdr2/source/pll_qdr_sim.v > Pll module for simulation /qdr2/source/pll_qdr_syn.v > Pll module for synthesis /qdr2/source/magma.v
Platform: | Size: 16384 | Author: liuxuemin | Hits:

CodeBus www.codebus.net